1. Field of the Invention
The present disclosure relates generally to a semiconductor fabrication and, more particularly, to a method for fabricating a transistor of a semiconductor device.
2. Background of the Related Art
As the integration degree in semiconductor devices advances, the width of a gate electrode, a thickness of a gate insulating layer, and the junction depth of source and drain regions decrease as well. Because a gate electrode made of polysilicon can not achieve a low resistance required in a fine interconnect, a new material and structure for the gate electrode is required to replace the conventional polysilicon. As a result, polycide made of transition metal-silicide has been suggested. However, the polycide gate electrode still has a difficulty in controlling the sheet resistance due to the polysilicon therein. The polycide gate electrode also has several problems such as an increase in an effective thickness of the gate insulating layer due to the gate depletion effect, boron penetration in a p+ polysilicon gate electrode and the variation of the threshold voltage due to the fluctuation of a dopant distribution.
Hence, to obviate such problems in polycide as described above, intensive research and development for a metal gate electrode is in progress. Because the metal gate electrode does not require any dopant, the gate depletion and the boron penetration can be effectively and efficiently prevented. In addition, the metal gate electrode can be used for both a PMOS and an NMOS transistor by using metals whose a work function corresponds to a mid bandgap of silicon. Here, such metals the metal include W, WN, Ti, TiN, Mo, Ta and TaN.
However, the metal gate electrode has still another problem such as a difficulty in the etch for patterning a desired gate electrode, plasma damages due to an etch and an ion implantation processes, and thermal damages due to later processes, which may detrimentally affect the characteristics of the semiconductor device.
Accordingly, to obviate such problems of the metal electrode as described above, a damascene gate process using the metal gate electrode has been suggested. The damascene gate process using the metal gate electrode generally comprises steps as follows. First, a dummy gate electrode made of polysilicon is formed. Next, an ILD (Inter-Layer Dielectric layer) is formed and the dummy gate electrode is removed. Next, a metal is filled where the dummy gate electrode has been removed and, subsequently, a planarization process such as a CMP (Chemical Mechanical Polishing) is performed. Finally, a metal gate electrode is completed. The resulting metal gate electrode has not been affected by the etching process and, therefore, various problems due to the etching process can be prevented. Moreover, the conventional semiconductor fabrication method can be adopted for the damascene gate process.
FIGS. 1a through 1g are cross-sectional views illustrating a MOSFET device in accordance with the conventional damascene gate process.
Referring to FIG. 1a, an active region is defined in a semiconductor substrate 1 by field oxide (not shown). A silicon oxide layer 2 is then grown on the active region. Subsequently, polysilicon 3 for a dummy gate electrode is deposited on the silicon oxide layer 2. A hard mask layer 4 is then deposited on the polysilicon 3.
Referring to FIG. 1b, a mask pattern 4a is formed by patterning the hard mask layer 4. Subsequently, the polysilicon 3 and the silicon oxide layer 2 are etched to form a dummy gate electrode 5 by using the mask pattern 4a. 
Referring to FIG. 1c, an LDD structure is formed adjacent to the dummy gate electrode 5 by implanting low concentration ions. Spacers 6 are then formed on the lateral faces of the dummy gate electrode 5. Source and drain regions with the LDD structure are formed around the dummy gate electrode 5 by implanting high concentration ions.
Referring to FIG. 1d, an ILD 7 is formed covering the resulting structure. Next, the ILD is then planarized by a CMP process until the top surface of the dummy gate electrode 5 is exposed. Subsequently, the exposed dummy gate 5 is removed.
Referring to FIG. 1e, a gate insulating layer 8 is formed along the surface of the resulting structure. A metal 9 for a gate electrode such as tungsten is deposited on the gate insulating layer 8.
Referring to FIG. 1f, the metal 9 for the gate electrode and the gate insulating layer 8 is polished until the IDL 7 is exposed.
However, in the conventional damascene gate process, as the width of the gate electrode decreases to less than 90 nm, an adequate sheet resistance of silicide on the gate electrode is difficult to achieve. Thus, Ni silicide which can be formed at a low temperature has been suggested to obtain the proper sheet resistance without the change of the junction depth of the source and drain regions. However, the Ni silicide also has a difficulty in ensuring a sufficient area without the change of the junction depth of the source and the drain regions.
In particular, as the width of the gate electrode decreases, the thickness of the silicide on the gate electrode increases to improve the resistance characteristic of the silicide and, thereby, a bridge effect arises between the gate electrode and the source and drain regions as well as a leakage current.